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Embedded Update
Using Slow ROMs

A fast clock can create timing hardships for ROM circuits. Good old fashioned EPROM just can't keep up without injecting a lot of wait states... which seems like a lousy way to diddle performance tradeoffs.

We've heard some rumblings that in the quest for speed some users ground their ROM's chip select, using OE to enable/disable the device. The reasoning is that OE is often almost twice as fast as CS. Let's look at a typical fast EPROM - Hitachi's HN27C256HG-70:

CE to output delay 70 nsec

OE to output delay 40 nsec

Address to output delay 70 nsec

Clearly OE is a lot faster than CS... but the device is just as slow decoding addresses as it is at responding to CS. That is, even with CS grounded you need at least a 70 nsec bus cycle to let the ROM decode the new address input.

Now, grounding CS does eliminate delays associated with CS generation; that is, if CS derives from decoded address lines (perhaps generated by a PAL), you've got to stretch the cycle by the time required by the PAL to do its thing. An awful lot of small systems, though, just run a single high order address line into the ROM's CS, so there's no extra decoding involved.

The moral: Check the entire system timing before making a rash assumption about wait states. ROMs are slow; for maximum performance figure on copying the ROM to RAM.