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Embedded Update
386EX Timing Issues

Intel's 386EX processor is taking the world by storm. It seems that an awful lot of folks who use the 188/186 today are considering the 386EX for future designs.

The part is attractively priced, and offers tremendous performance. It's a good bet for many applications, especially since even in real mode it's substantially faster than its older cousins. The 386EX is a two T-state machine; if your memory is fast enough to run without waits then your system can scream.

The 2 T-state design makes some pretty severe demands on your memory and I/O design, though. At 25 Mhz (50 Mhz clock) there's only 44 nsec between when the addresses become valid and when you've got to present the data. It makes sense to inject a single wait state, buying another 40 nsec of margin.

The good news is that the processor has a very powerful wait state generator on-board. We figure that most users will run at least a single wait state to keep their memory costs under control.

Unfortunately, a bug in the current revision of the part gives no data hold time after the write signal goes away. Essentially, this means you'll have to fabricate a pseudo-write to your RAMs; one that disappears just a tad before the addresses and Write go invalid to meet data hold times on the RAMs themselves.

Intel's recommended solution (see their faxback service for details) works, but requires fairly smart circuit. It essentially tracks the CPU's bus cycles, disabling write just before the cycle ends.

Since each writable device (RAM, I/O) may use a different number of wait states, the circuit must dynamically adapt to each bus cycle to end the cycle at the right spot no matter how long it is stretched by the READY logic.

These waits are usually generated on-board the CPU using the internal wait state generator. Unlike most other Intel CPUs, READY is a bi- directional line. To assert a wait, you drive it in. When the internal wait state generator is asserting wait, READY drives out so your smart circuit will know that the cycle is about to end. An extra signal, LBA, is the traffic cop that indicates which way READY is pointed.

Make you wonder why they didn't simply use a READY IN and a READY OUT.

The evaluation board Intel supplies implements the circuit in PLDs. We recommend you get the board and swipe the design.

The important thing to note is that YOU WILL NOT HAVE A RELIABLE DESIGN unless you follow these guidelines.

Intel is promising an update that will give 5 nsec of data hold time after Write. This isn't much; when the new parts are available be really sure to check your timing, and the hold requirements of the RAMs, to insure 5 nsec is enough.

Stretched Cycles

We have seen one odd characteristic of the part: Jumps, Calls, and other transfers of control (especially between segments) stall the processor for a dozen or so clock cycles. On a logic analyzer you'll see Read go away, and then nothing happen for quite a while before the CPU starts fetching from the new address. The 8088/6 and 80188/6 don't do this.

In protected mode the CPU might have to fetch new descriptors on any long transfer. This is not the case in real mode, so we're left a little puzzled about what is going on.