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186 Reset Circuits

Abstract
A processor's RESET input is surprisingly tricky to manage. If you're using a 186 processor - particularly one that is surface-mounted to the PC board - take a minute to read this over.

Voltage Levels Surprise! Most processors don't accept TTL signal levels for the RESET input. If you drive RESET with a gate or logic device there's a good chance that the system won't start reliably. Here are minimum legal "one" levels, for Vcc=5.0:



Note that many of the Intel parts are not TTL compatible on any of the inputs, with minimum legal "ones" of 3.5 volts. Be sure that anything driving the pins has CMOS voltage levels.

Don't use a 74xx or PAL or similar device to drive reset unless you're quite sure the minimum "one" it generates is at least the voltage listed above. It's a good idea to put a fairly hefty pull-up resistor on your RESET drive circuit (assuming it's not a simple RC timer).

Slew Rate

Some 186 processors will not start reliably unless RESET slews from a zero to a one at some minimum rate. The 186XL, in particular, is hopelessly confused by a simple RC RESET circuit. Others, like the Am186EM and ES, include Schmidt triggers that clean up slowly ramping inputs. We suggest driving RESET on all of these processors with a fast clamp device designed expressly for this purpose - such as the Dallas Semiconductor's DS1232. These devices have open collector outputs, so a simple pull-up fulfills the voltage requirements listed above - and have very snappy AC response.

Brown-outs and RAM Reliability

Simple RC circuits do nothing to protect data when power is lost. Your system's elaborate battery-backed up RAM circuit will be defeated by a CPU running amok as power dies off. Consider: power fails very slowly compared to the instruction speed of any modern processor. The processor is guaranteed to run correctly only within a limited voltage range - say, 4.75 to 5.25 volts. It will, however, do something as power ramps down from 5 to 4 to 3 and eventually to zero. Sooner or later it will write over your protected RAM area.

A decent clamp circuit will drive the CPU into RESET - a safe, idle state - as soon as power falls outside of the legal range. Your RAM contents get power-down/brown-out protection. Do be sure to put pull-ups on all write lines from the processor, as these float during RESET, and so may create erratic writes to the system's RAM.

Today there's no excuse for not using a commercial clamp circuit. Consider the advantages:

Correct slew rate logic "one" condition (with appropriate pull-up) insic power-down/brown-out protection.

Once Mode

How do you connect an in-circuit emulator to a processor that is soldered onto a circuit board? If you could somehow tri- state all of the processor's pins, the emulator could clip over the device, connecting to each lead, using the soldered- down CPU merely as a mechanical anchor. The emulator's processor could then control your system.

Neither RESET nor HOLD float all of the CPU's pins. The solution: ONCE - pronounced "ahnce" - mode, which does indeed tri- state every pin on the device.

So, clip your ICE's pod over the CPU chip, drive the processor into ONCE mode, and the emulator takes complete control of your target system. It's a slick solution to a tough problem. Provided, of course (there's always a gotcha!) that your target system's design is compatible with ONCE mode.

First, a little background. Emulators drive the surface-mounted processor into ONCE mode by asserting RESET while driving A19 low (on the 186EB and 186EC), or while driving both UCS and LCS low (all other variants). The CPU will exit ONCE mode if it ever sees a RESET pulse without the corresponding A19 or UCS/LCS assertions.

Clearly, an emulator should sense when your system asserts reset, and simultaneously drive the ONCE mode pins low. If, say, you press your target's RESET button the emulator will do what is required to keep the CPU in ONCE mode.

In addition, resets generated by the emulator must assert the RESET line as well as the ONCE mode lines to keep the CPU in ONCE mode.

But these two goals conflict. A single wire - RESET - is driven by both your target hardware and the emulator. Though Softaid's emulators drive RESET with an open collector buffer to avoid problems, a conflict still exists if your target system uses an active driver.

(Though we've recommended against using RC reset circuits here, clearly an RC is equivalent to an open collector "device" so there is no conflict. However, the very slow ramp creates another problem: the CPU will detect reset active at a different time than the emulator, which will likely remove the ONCE mode assertion prematurely. The solution: remove the capacitor when working with an emulator.)

If your system uses an active, non-open collector, driver, you can remove your RESET driver when debugging to eliminate the conflict. Or, never use the emulator to issue resets. Instead, press the button on your target. The emulator will properly sense RESET's assertion and keep the system in ONCE mode, but won't try to overdrive the buffer. You could also put a series resistor right after the buffer. 47 ohms will most likely not create voltage or drive problems, yet will permit both the emulator and the buffer to assert RESET independently and reliably.

The UEM and Reset

Softaid's UEM emulator includes a circuit to "mask", or ignore, target resets. There are cases - like, if a watchdog timer drives RESET - where it's handy to disable this input under software control.

The emulator always ignores target reset when it's not running your code. If it's emulating (executing code) things change: if the RESET signal is masked, it will ignore the input. If not masked, then it accepts RESET, drives the emulator's processor through a complete reset cycle, and resumes from the reset vector.

In any case, the UEM will assert the ONCE signals to keep the target processor in ONCE mode.

Copyright 1996, Softaid, Inc.