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HMI
Emulator and BMD Application Note
The Motorola MC68HC12 Microprocessor
Introduction
The purpose of this application note is to provide user level
documentation to aid in the use of HMI products with Motorola’s
MC68HC12 microprocessor.
The MC68HC12 BMD
External Clip-Leads
E-Clock and Ground
Note: Current BMDs ship with a VIOLET colored E-Clock lead
and a BLACK colored Ground lead. Some early versions shipped
with an E-Clock lead that was BLACK and a Ground lead that was
BROWN. This documentation applies equally to both versions.
The background port of the Motorola MC68HC12 requires a clock
signal that is of the same frequency as that of the CPU’s E-clock,
which is one-half the processor’s crystal frequency. However,
Motorola did not include this signal in the 68HC12’s BDM port
specification. The HMI 68HC12 BMD includes an external clip-lead
that can be attached to the ECLK/PE4 pin of the target system’s
CPU. This imposes the limitation that the ECLK/PE4 pin must
be used as the ECLK, and requires that the NECLK bit (bit 4
of the PEAR register) be set to ‘0’, and that either the IVIS
bit (bit 3 of the MODE register) be set to ‘1’, or that the
ESTR bit (bit 4 of the MODE register) be set to ‘0’. The HMI
68HC12 BMD will set the target CPU to the correct values at
reset.
Attach the lead with the VIOLET clip to the E-Clock signal from
the target system. It is recommended that you also attach the
lead with the Ground clip to a nearby ground, as this will greatly
reduce the level of noise injected into the BMD’s circuit from
the clock signal.
If it is not possible to run the target system in this configuration,
the user can supply a separate clock of the same frequency.
It is not necessary that this clock be synchronized to the CPU’s
E-Clock. However, it must be of the same frequency (+/- 10%).
Mode Selection (RED and ORANGE clips)
The Motorola MC68HC12 is designed so that the processor will
only come out of reset in background debug mode if it is booted
in special single chip mode. In any other mode the processor
can not be placed into background debug mode until after it
has come out of reset and run some of the user’s code.
For systems that are designed to run in normal single chip mode,
the HMI 68HC12 BMD will drive the BKGD pin to place the CPU
in special single chip mode out of reset, and then switch back
to normal single chip mode. However, for systems that are designed
to operate in either of the expanded modes this is not possible
using the signals provided in the MC68HC12’s BDM port specification.
As a workaround, the HMI BMD provides two additional clip-leads
that can be attached to the target system mode lines. The HMI
BMD will drive the mode lines with the appropriate levels to
boot the CPU in special single chip mode, and then switch the
CPU to the correct mode after a reset. The ORANGE clip should
be attached to the target system’s MODA signal, and the RED
clip should be attached to the target system’s MODB signal.
The HMI BMD must be able to drive these signals low, so if a
signal is tied high it must be done though a pull-up resistor.
Note that these leads should be attached to the target system
regardless of the mode as the HMI BMD reads these signals after
a reset in order to determine in which mode the target system
is designed to operate.
Power Source
Earlier BMDs received input power from the target board via
the six pin background port connection. In these cases, the
target board must be capable of supplying 200 milliamps at 3
to 5 volts DC. More recent BMDs can be powered by an external
power source plugged into the BMD. Switching from target supplied
power to the external power supply requires changing an internal
jumper. (See separate documentation.)
Microprocessor Specifics
MC68HC912B32 and MC68HC912BC32
The INITRG Register
The INITRG register determines the location of the peripheral
register memory block. Because the register moves along with
the memory block, SourceGate is not able to determine on its
own where the peripheral registers are located. For this reason,
users must utilize the S_PMBA (Set Peripheral Module Base Address)
command to let SourceGate know where the registers are located.
SourceGate’s Peripheral Register feature will otherwise not
function properly. If INITRG is modified by executed code, then
the S_PMBA command must be issued after the code is executed.
The following is an example:
s_pmba
<new address>
/2 ; pause 2 seconds while it takes effect
If INITRG is modified directly via SourceGate, then follow the
below sequence in the Command window when changing INITRG.
s_pmba
<old address>
/2 ; pause 2 seconds while it takes effect
exr /initrg = <new value>
s_pmba <new address>
/2 ; pause 2 seconds while it takes effect
Processor Breakpoints
Please Note: Only the software breakpoints are available
at this time. For this reason the SBE command must be used in
the setup command file for flash programming. Otherwise it will
fail.
The processor’s two internal breakpoints are available within
SourceGate as two hardware type breakpoints. These breakpoints
are not available at the same time that software breakpoints
are available. SBE (Software Breakpoint Enable) is used to enable
the software breakpoints. SBD (Software Breakpoint Disable)
is used to enable the hardware breakpoints. Refer to the user
manual for enabling and disabling software breakpoints. (The
S_PMBA command must be issued as described above for SourceGate
to be able to properly use the processor breakpoints.) The processor’s
breakpoint feature is affected by an opcode’s even or odd address,
and whether the opcode was loaded by an eight bit or a 16 bit
instruction fetch (breakpoints at odd addresses within a 16
bit opcode fetch are ignored). Two 68HC12 specific commands
have been added in support of this characteristic; S_CPUBP_LSBM
and S_CPUBP_ODDA. Both are described in the below table. The
commands apply only to processor breakpoints, and their settings
are recorded in the processor’s .ini file.
| Command |
Description |
| S_CPUBP_LSBM |
Report
on the current setting of the Least Significant Bit Mask
option. |
| S_CPUBP_LSBM
0 |
Do
not alter the least significant bit of breakpoint addresses.
|
| S_CPUBP_LSBM
1 |
Force
the least significant bit of breakpoint addresses to zero.
|
| S_CPUBP_ODDA
|
Report
on the current setting of the Odd Address Permission option.
|
| S_CPUBP_
ODDA 0 |
Do
not permit the use of odd breakpoint addresses. |
| S_CPUBP_
ODDA 1 |
Permit
the use of odd breakpoint addresses. |
Development Boards
Axiom Manufacturing CME12B32
Flash/EEPROM Programming
Programming of the flash and EEPROM internal to the MC68HC912B32
requires that a jumper be placed across jumper block VPP_EN.
BMD Operating Power
This development board requires no modification in order to
be able to supply the BMD’s operating power through the six
pin background port connection. Those BMDs with an external
power jack should be powered externally rather than by the target
board.
Motorola M68HC12B32EV
Flash/EEPROM Programming
Programming of the flash and EEPROM internal to the MC68HC912B32
requires that jumper block W8 be powered by +12VDC and that
the jumper on jumper block W7 be placed across the center and
VPP posts.
BMD Operating Power
This development board requires no modification in order to
be able to supply the BMD’s operating power through the six
pin background port connection.
Flash and EEPROM Programming
MC68HC912B32 and MC68HC912BC32
The programming algorithms for the flash and EEPROM internal
to these processors have specific target configuration requirements
in order to program these devices successfully. If these requirements
are not satisfied, then reprogramming efforts will fail. These
requirements are as follows:
1. The peripheral registers must be located at 0x4000.
2. The chip’s internal RAM must be located at 0x0.
3. All interrupts must be disabled.
4. The internal EEPROM must be located at 0x4D00.
5. The internal flash memory must be located at 0x8000.
6. The internal timer must be configured for a frequency of
512KHz .
Flash Programming
No special consideration are required when reprogramming the
internal flash memory. However, the RAM address must be given
as 0x0 and the flash address as 0x8000. The flash memory size
is 8 bits wide by 32K bytes deep (0x8000). Configure the target
board with the setup file given below.
EEPROM Programming
Special consideration is required when reprogramming the internal
EEPROM memory. This is because the EEPROM’s size is 768 bytes;
a size not normally accommodated by SourceGate. To work around
this, SourceGate’s flash programming feature must be told that
the device is 8 bits wide by 1K bytes deep, and located on a
1K boundary (0x4C00). The programming algorithm was designed
to handle this, and will ignore any memory reference outside
the range of 0x4D00 to 0x4EFF. When invoking the programming
operation specify the RAM address as 0x0, the flash address
as 0x4C00, and the size as 1K bytes (0x400). Configure the target
board with the setup file given below.
Configuration Setup File
The SourceGate command file given below will configure the processor
for flash and EEPROM programming operations.
; Configure the 68HC912B32/68HC912BC32
in preparation for FLASH or
; EEPROM programming. This setup file is written specifically
to
; work for two different evaluation boards; Motorola's
; M68HC912B32EVB evaluation board, and Axiom Manufacturing's
; CME12B32 evaluation board, both of which runs at 8MHz. On
this
; chip VFP must be powered by +12V.
; THIS FILE MUST BE USED!!!!!!!!!
; THE FLASH ALGORITHM IS SPECIFICALLY WRITTEN TO RUN ON THIS
CHIP'S
; INTERNAL MEMORY. IT IS WRITTEN TO WORK SPECIFICALLY WITH THE
; CONFIGURATION PRODUCED BY THIS COMMAND FILE.
; IN THE SG FLASH PROGRAMMING OPTIONS, SET THE FLASH AND RAM
; ADDRESSES AS SPECIFIED BELOW.
rs
s_cpubp_lsbm 0
s_cpubp_odda 1
s_pmba 0
/ 2
exr /INITRG = 40 ; put register map at 0x4000
s_pmba 4000
/ 2
sbe ;enable software breakpoints
; Initialize the peripheral registers.
; RAM is at 0x0. <<<<=======================================
;exr /MODE = 19 ; put in Special Single Chip Mode
exr /INITRM = 00 ; put internal RAM at 0x0
exr /RTICTL = 60 ; disable RTI
exr /COPCTL = 08 ; disable COP
exr /INTCR = 20 ; disable external interrupts
f[b] 4020 4020 00 ; disable breakpoints
exr /PWEN = 00 ; disable the Pulse Width Modulator
exr /ATDCTL2 = 00 ; disable the Analog-to-Digital Converter
exr /SC0CR2 = 00 ; disable the Serial Comm. Interface
exr /SP0CR1 = 04 ; disable the Serial Peripheral Interface
exr /BCR1 = E0 ; disable the Loopback Modes
; Internal EEPROM
; The internal EEPROM is being located to 0x4D00.
; The user MUST specify that it is located at 0x4C00. <<<<=========
exr /INITEE = 41 ; enable and locate at 0x4D00
exr /EEMCR = FC ; stop in WAIT mode, enable mod bits, use system
clock exr /EEPROT = 00 ; modified at programming time
exr /EEPROG = 00 ; modified at programming time
; Internal FLASH
; The internal flash is being located to 0x8000. <<<<==============
exr /MISC = 0F ; enable and locate FLASH at 0x8000
exr /FEELCK = 00 ; enable write to FEEMCR
exr /FEEMCR = 00 ; enable mods to boot block
; Timer
exr /TMSK1 = 00 ; disable hardware interrupts
exr /TMSK2 = 04 ; disable overflow interrupt, PCLK / 16: 8MHz
/ 16 = 512KHz
exr /PACTL = 00 ; disable all, use PCLK / x
exr /TSCR = E0 ; enable timer
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